1. Field of the Invention
The present invention relates to flip-chip type integrated circuit devices with decreased susceptibility to memory loss caused by alpha particles. Particularly, the bond pads of the device of the present invention are positioned on the device in a manner which significantly reduces or eliminates the tendency of alpha particles emitted from solder bumps or balls formed thereon to enter the memory arrays of the device. More particularly, the bond pads of the integrated circuit of this invention are positioned directly over the logic portions of the device. Another aspect of the present invention includes the placement of bond pads on the active surface of a DRAM integrated circuit, over the logic circuits thereof. The present invention also relates to integrated circuit devices which have a reduced length of circuitry between the logic portions thereof and the bond pads operatively connected therewith.
2. State of the Art
Integrated circuits (ICs), also known as xe2x80x9cchipsxe2x80x9d or xe2x80x9cdicexe2x80x9d, which use solder-type inverted xe2x80x9cflip-chipxe2x80x9d or Controlled Collapse Chip Connection (C4) bonding technology, are well known in the industry. Many flip-chip integrated circuits are bonded to the substrate by lead/tin (Pb/Sn) solders, which are known to emit helium nuclei, also referred to as alpha particles. Flip-chips which include bond pads in area arrays are subject to alpha particle penetration, which can create a xe2x80x9ccloudxe2x80x9d in the die surface. Such clouds include millions of electron-hole pairs along the track of the alpha particle, which discharge the storage cell capacitors, the bit-lines, particularly if they are diffused, and the sensing nodes in the sense amplifiers of the memory cell arrays of the integrated circuit. However, errors induced by alpha particles are related almost exclusively to the amount of stored charge. In dynamic random access memories (DRAMs), alpha particles cause a loss of memory, but do not physically damage the integrated circuit""s memory cells. This is referred to as a xe2x80x9csoft errorxe2x80x9d since there is no physical damage to the memory cell, but merely a temporary loss of charge. However, this problem results in few flip-chip DRAMs. Many in the art wire bond a die to an interposer, then attach the interposer to a substrate using flip-chip technology.
Referring to FIG. 1, in many flip-chip memory circuits, the bond pads are positioned in a row and column array, referred to as an area array, across the active surface of the chip. Area arrays are often arranged in standardized footprints in order to match to corresponding sites on a substrate. In many such arrays, several of the bond pads are located over memory cells, which are known by those of skill in the art to be the more fragile portions of a memory circuit.
Many flip-chip DRAM integrated circuits are coated with a relatively thick coating to absorb alpha radiation and lower the soft error rates; such coatings include without limitation polyimides and glasses, such as borophosphosilicate glass (BPSG), phosphosilicate glass (PSG) and borosilicate glass (BSG). When glass is used as the coating material, the layer may be as much as 6 mils thick. This coating can be applied either to the chip during the assembly process when it is known as xe2x80x9cchip coatxe2x80x9d or xe2x80x9cdie coatxe2x80x9d, or it can be applied to the wafer during the manufacturing process when it is called a xe2x80x9cwafer coatxe2x80x9d. Alternatively, because thick coats of such materials tend to slow heat transfer away from the flip-chip die, metal layers may be used to shield the memory arrays of DRAM dice from alpha particle penetration. A layer of alpha radiation-absorbent material may also be injected between the integrated circuit on the active surface of a flip-chip die and a carrier substrate to prevent alpha particles from penetrating areas of the integrated circuit adjacent to the bond pads.
Several disadvantages are inherent with flip-chips having bond pads disposed in area arrays. First, additional circuitry is necessary to operatively connect the bond pads of such an area array to associated logic portions of the integrated circuit. Second, alpha radiation-absorbent layers, and therefore additional manufacturing steps, are often necessary to shield the integrated circuit""s memory cells from alpha radiation emitted by the solder balls formed on and attached to the bond pads. Third, because many of the bond pads overlay memory cells, much of the weight of the integrated circuit is supported by the more fragile portions of the chip. Finally, due to the continual increase of integrated circuit densities, size and pitch limitations are potential problems with flip-chips having area arrays.
It is well known to those of ordinary skill in the art that longer circuit trace runs increase power requirements. Longer traces also increase the amount of heat generated during the operation of an integrated circuit. When longer traces are used, it takes electrons longer to flow from one point to another. Thus, the overall speed of an integrated circuit is increased as the length of circuitry between logic portions and the bond pads is reduced. Thus, integrated circuits with bond pads removed from their associated circuitry are undesirable.
The use of alpha-particle absorbing layers is also undesirable in that such layers require an additional step in the manufacture of the integrated circuit. Additional manufacturing steps introduce an increased likelihood of damaging each chip, as well as increased manufacturing costs. Similarly, the placement of bond pads on the active surface over memory cells increases the likelihood that an integrated circuit will be damaged by impacts or loads placed on the die during bonding to a carrier substrate, especially in the case of memory integrated circuits, which tend to be larger and heavier than many other integrated circuits.
Many integrated circuits include bond pads which are positioned around the outer periphery of the device. Wire bonded integrated circuits and flip-chip integrated circuits with peripheral bond pads (shown in FIG. 2) are examples of such integrated circuits. Although integrated circuits employing such bond pad placement are not subject to as many soft errors as area array flip-chips, peripheral bond pad placement requires the use of electrical circuit traces, also referred to merely as xe2x80x9ctracesxe2x80x9d, between the bond pad and the corresponding logic circuits of the chip. In many of the integrated circuits with peripheral bond pads, the bond pads are positioned over dead areas of the chipxe2x80x94areas which include neither logic nor memory. When solder is used to connect such an integrated circuit to a substrate, constraints on the minimum possible size and spacing, or xe2x80x9cpitchxe2x80x9d, of solder bumps limit the number of connections that can be made with the substrate.
The disadvantages of extended circuit traces have been discussed above. Integrated circuits requiring peripheral bond pads are also undesirable because the peripherally located bond pads are positioned over areas of the chip which do not include logic circuits or memory cell arrays. Thus, a significant amount of the surface area of the chip is not utilized, necessitating a larger integrated circuit than would otherwise be required. Therefore, the chip density per wafer is not maximized with such integrated circuit configurations.
Peripherally bonded integrated circuits which are connected to a substrate with solder bumps also include a limited number of bond pads due to minimum physical size limitations of a solder ball. However, even as the internal circuit element sizes of integrated circuits decrease, the number of connections required may either increase or, at best, remain the same. Thus, ball size and pitch limitations in such integrated circuits prevent further reduction in the die size of integrated circuits with peripheral bond pads even if more active circuit elements could otherwise be accommodated.
Alpha particles have a known energy range. Thus, many integrated circuit manufacturers have attempted to design memory cells with sufficient capacitance to enable the charge generated from an alpha hit to be absorbed without changing the value of that cell from a one to a zero. The increased capacitance of such cells improves the soft error rate in DRAMs.
However, increasing the capacitance of an integrated circuit requires a redesign of the integrated circuit, which is undesirable to many manufacturers. For example, in order to increase the capacitance of an integrated circuit, the gate oxide thickness must be scaled down as the DRAM cell is scaled laterally, or a gate material which has a higher dielectric constant than silicon dioxide must be used, including, without limitation, silicone nitride, ferro electric materials, or others.
What is needed is an integrated circuit device which is of reduced susceptibility to memory loss caused by alpha particles without the requirement of a surface coating for protection from alpha particles. Further, more efficient use of the die xe2x80x9creal estatexe2x80x9d is needed, as is an integrated circuit with flip-chip connections which are not pitch-limited. A more robust chip, providing greater speed, with lower power requirements and lower heat output is also desirable.
The integrated circuit device of the present invention addresses each of the foregoing needs. The bond pads of the device of the present invention are positioned over the surface of the device rather than along the outer periphery thereof, which permits a decrease in the size of the die compared to peripherally bonded integrated circuits, making more efficient use of the surface area of the die and permitting use of a given memory capacity with a smaller die. Preferably, the bond pads of the device are arranged over the relatively durable logic areas thereof. Thus, the integrated circuit of the present invention withstands mechanical fatigue better than many comparable devices which are currently known and used in the industry. The bond pads are positioned such that the length of the electrical traces, or connective circuitry, between a bond pad and its corresponding logic component is significantly reduced, or such electrical traces are eliminated, which decreases the overall resistance of the circuit, and thus its power requirements, which in turn reduces the heat generated during operation of the integrated circuit. The reduced length of the circuit traces in the device of the present invention also decreases the amount of time it takes an electrical impulse to travel from the logic area to the bond pad, thus increasing the potential speed of the device.
The bond pads of the integrated circuit device of the present invention are positioned over the logic areas of the device, rather than over the memory array(s). When the bond pads of the device are attached to a substrate, such as a printed circuit board or other substrates which are well known in the industry, with a lead/tin (Pb/Sn) solder, alpha particles emitted from the solder are unlikely to enter the laterally-offset memory array and create xe2x80x9csoftxe2x80x9d errors therein. Thus, it is a consequent advantage that the integrated circuit device of the present invention is less susceptible to memory loss caused by alpha particles than presently known integrated circuits. Further, the device of the present invention requires little or no protective coating over the active surface due to the placement of bond pads over the logic areas of the device. As a result, no protective coatings such as the protective metal shields, polyimide layers, glass layers and other protective layers that are used in many flip-chip integrated circuits are necessary on the device of the present invention.
The integrated circuit die according to this invention includes bond pads spaced over large portions of the active surface thereof, rather than being located at the die periphery over a xe2x80x9cdead spacexe2x80x9d portion of the die which is used for neither memory nor for logic. Consequently, the die of the integrated circuit of this invention need not include dead space for positioning the bond pads, so that the overall physical size of the die for a given memory capacity may be reduced.
In a preferred embodiment of the device of the present invention, the placement of bond pads over the more durable logic portions of the integrated circuit improves the device""s ability to withstand mechanical stress when compared with flip-chip integrated circuits which include bond pads positioned over memory cell arrays.
The apparatus of the present invention may be fabricated at the semiconductor die level, at the wafer level, or at a partial wafer level wherein a partial wafer includes a plurality of die locations. As used herein, the term xe2x80x9cwaferxe2x80x9d includes conventional, disc-shaped substrates of semiconductor material (silicon, gallium, arsenide, etc.) as well as silicon-on-insulator (SOI) substrates such as silicon-on-glass (SOG), silicon-on-sapphire (SOS), and others known in the art.
Other advantages of the present invention will become apparent to those of ordinary skill in the pertinent art through a consideration of the appended drawings, taken in conjunction with the ensuing description.